1. Field of the Invention
The present invention relates generally to a split-gate flash memory cell and its memory array and, more particularly, to a self-aligned split-gate flash memory cell and its contactless flash memory array for high-speed erasing operation in high-density mass storage applications.
2. Description of Related Art
The flash memory cells of the prior arts, based on the cell structure, can be categorized into two groups: a stack-gate structure and a split-gate structure. The stack-gate flash memory cell is in general programmed by channel hot-electron injection (CHEI), the programming power is large and the programming efficiency is low. In general, the stack-gate length is defined by a minimum-feature-size (F) of technology used, the cell size of a stack-gate flash memory cell is relatively smaller and is, therefore, favorable for high-density mass storage applications. However, the stack-gate length is difficult to be scaled due to the punch-through effect if the channel hot-electron injection is used as a programming method. Moreover, the applied control-gate voltage for programming is difficult to be scaled due to the coupling ratio; the erasing speed based on Fowler-Nordheim tunneling between the floating-gate and the source diffusion region becomes poor due to the scaled tunneling area; and the over-erase problem needs a complicate control circuit for verification.
The split-gate flash memory cell is in general programmed by mid-channel hot-electron injection, the programming power is relatively smaller and the programming efficiency is high. However, the cell size of a spit-gate flash memory cell is much larger than that of the stack-gate flash memory cell and is, therefore, usually used in low-density storage applications. A typical split-gate flash memory device is shown in FIG. 1A, in which a floating-gate layer 111 is formed by local-oxidation of silicon (LOCOS) technique and the floating-gate length is defined in general to be larger than a minimum-feature-size of technology used due to the bird""s beak formation; the control-gate 115 is formed over a LOCOS-oxide layer 112 and a thicker select-gate oxide layer 114; a poly-oxide layer 113 is formed over a sidewall of the floating-gate layer 111; a source diffusion region 116 and a drain diffusion region 117 are formed in a semiconductor substrate 100 in a self-aligned manner; and a thin gate-oxide layer 110 is formed under the floating-gate layer 111. From FIG. 1A, it is clearly visualized that the cell size is larger due to the non-self-aligned control-gate structure; the gate length can""t be easily scaled down due to the misalignment of the control-gate 115 with respect to the floating-gate 111; the field-emission tip of the floating-gate layer 111 is difficult to be controlled due to the weak masking ability of the bird""s beak oxide; and the coupling ratio is low and higher applied control-gate voltage is required for erasing electrons from the floating-gate tip to the control gate 115.
FIG. 1B shows another split-gate structure, in which the floating-gate layer 121 is defined by a minimum-feature-size of technology used; a thin tunneling-oxide layer 120 is formed under the floating-gate layer 121; a select- gate dielectric layer 122 is formed over the select-gate region and the exposed floating-gate layer 121; a control-gate layer 123 is formed over the select-gate dielectric layer 122; a source diffusion region 124 and a double-diffusion drain region 125,126 are formed in a semiconductor substrate 100. From FIG. 1B, it is clearly visualized that similar drawbacks as listed for FIG. 1A are appeared although the coupling ratio is slightly improved by the select-gate dielectric layer 122 used. However, the erasing site is located at the thin tunneling-oxide layer 120 between the floating-gate layer 121 and the double-diffused drain region 125,126, the erasing voltage is much higher than that of a stack-gate structure due to the smaller coupling ratio.
It is therefore an objective of the present invention to offer a self-aligned split-gate flash memory cell having a cell size being smaller than 4F2.
It is another objective of the present invention to offer a higher coupling ratio for a self-aligned split-gate flash memory cell.
It is a further objective of the present invention to provide a source-side erase structure for a self-aligned split-gate flash memory cell and its contactless flash memory arrays to increase the erasing speed.
It is yet another objective of the present invention to offer two contactless array architectures for forming self-aligned split-gate flash memory arrays.
Other objectives and advantages of the present invention will be apparent from the following description.
A self-aligned split-gate flash memory cell of the present invention is formed on a semiconductor substrate of a first conductivity type having an active region isolated by two parallel shallow-trench isolation (STI) regions. A cell region can be divided into three regions: a common-source region, a gate region, and a common-drain region, wherein the gate region is located between the common-source region and the common-drain region. The common-source region comprises a common-source diffusion region; a first sidewall dielectric spacer acting as a tunneling-dielectric layer being formed over a sidewall of the gate region and on a portion of a first flat bed being formed by a shallow heavily-doped source diffusion region of a second conductivity type formed within a common-source diffusion region in the active region and two etched first raised field-oxide layers in the two parallel STI regions; a common-source conductive bus line acting as an erase anode being formed over the first flat bed outside of the first sidewall dielectric spacer; a first auxiliary sidewall dielectric spacer being formed over the first sidewall dielectric spacer and on a portion of the common-source conductive bus line; a auxiliary common-source conductive bus line being formed over a common-source conductive bus line outside of the first auxiliary sidewall dielectric spacer; and a first planarized thick-oxide layer being formed over the auxiliary common-source conductive bus line. The common-drain region comprises a second sidewall dielectric spacer being formed over another sidewall of the gate region and on a portion of a second flat bed being formed by a shallow heavily-doped drain diffusion of a second conductivity type formed within a common-drain diffusion region in the active region and two etched second raised field-oxide layers in the two parallel STI regions; a common-drain conductive bus line or a common-drain conductive island being formed over the second flat bed outside of the second sidewall dielectric spacer; and a second planarized thick-oxide layer is formed over the common-drain conductive bus line. The gate region comprises an integrated floating-gate layer having a major floating-gate layer formed on a first gate-dielectric layer in a portion of the active region near the common-source diffusion region and two extended floating-gate layers separately formed on a portion of the two first raised field-oxide layers in the two parallel STI regions with a first intergate-dielectric layer being formed on its top and a second intergate-dielectric layer being formed over its inner sidewall; a second gate-dielectric layer being formed in another portion of the active region near the common-drain diffusion region; and an elongated planarized control/select-gate conductive layer or a planarized control/select-gate conductive island being at least formed over the first/second intergate-dielectric layers and the second gate-dielectric layer.
The self-aligned split-gate flash memory cell of the present invention as described is used to implement two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array. The contactless NOR-type flash memory array comprises a plurality of common-source conductive bus lines being formed alternately and transversely to a plurality of parallel STI regions, wherein each of the plurality of common-source conductive bus lines is formed between a pair of first sidewall dielectric spacers and on a first flat bed being alternately formed by a shallow heavily-doped source diffusion region of a second conductivity type formed within a common-source diffusion region and an etched first raised field-oxide layer; a plurality of common-drain conductive islands being at least formed over a plurality of active regions in each of the common-drain regions between the plurality of common-source conductive bus lines, wherein each of the plurality of common-drain conductive islands is formed between a pair of second sidewall dielectric spacers and on a shallow heavily-doped drain diffusion region of a second conductivity type formed within a common drain diffusion region in the active region and a portion of etched second raised field-oxide layers in the nearby parallel STI regions; a plurality of self-aligned split-gate flash memory cells being formed between each of the plurality of common-source conductive bus lines and its nearby common-drain conductive islands with an elongated planarized control/select-gate conductive layer being acted as a word line; and a plurality of bit lines integrated with the plurality of common-drain conductive islands being simultaneously patterned and etched by a plurality of hard masking layers being transversely to the plurality of common-source conductive bus lines.
The contactless parallel common-source/drain conductive bit-lines flash memory array of the present invention comprises a plurality of common-source conductive bus lines and a plurality of common-drain conductive bus lines being formed alternately and transversely to a plurality of parallel STI regions, wherein each of the plurality of common-source/drain conductive bus lines is formed between a pair of first/second sidewall dielectric spacers and on the first/second flat bed being alternately formed by a shallow heavily-doped source/drain diffusion region of a second conductivity type formed within a common-source/drain diffusion region and an etched first/second raised field-oxide layer; a plurality of self-aligned split-gate flash memory flash memory cells being formed between each of the plurality of common-source conductive bus lines and its nearby common-drain conductive bus lines; and a plurality of word lines integrated with a plurality of planarized control/select-gate conductive islands being simultaneously patterned and etched by a plurality of hard masking layers being transversely to the plurality of common-source/drain conductive bus lines.